Job Description
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want to join us in these pursuits? Join us to help deliver the next groundbreaking Apple product!
As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as well as developing, maintaining and improving our Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC) and Static Timing Analysis (STA) constraints and methodology for our CPUs across multiple design sites.
Description
In this role, you will be:
• Responsible for developing, improving, and maintaining the CDC and RDC sign-offs for CPU designs
• Working with RTL and DV teams to recommend System Verilog assertions needed to support CDC/RDC/STA constraints and assumptions
• Highlighting to the RTL team any CDC/RDC issues and recommending solutions to them and educating them on CDC/RDC issues and the importance of structurally safe solutions to each issue
• Responsible for developing, enhancing, and maintaining key STA checks and associated sign-offs for our CPUs including things needed to complement CDC/RDC
• Responsible for debugging vendor tool problems and collaborate with designers to help solve their problems
• Working closely with EDA vendor representatives to drive improvements and new methodologies
• Working closely with RTL, Verification, CAD, and Physical Design teams
Minimum Qualifications
- Minimum BS and 10+ years of relevant industry experience
- Experience with Clock-Domain Crossing (CDC) and Reset Domain Crossing (RDC)
- Scripting experience in Tcl or Perl
- Experience in Verilog
Key Qualifications
Preferred Qualifications
- Experience in SystemVerilog Assertions (SVA) and Design Verification (DV) Simulations
- Experience in multi-clock-domain RTL design
- Knowledge in Spyglass, VC-Static, PrimeTime, or Meridian is a plus
Education & Experience
Additional Requirements
Pay & Benefits
- At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $175,800 and $312,200, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
- Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.
In this role, you will be:
• Responsible for developing, improving, and maintaining the CDC and RDC sign-offs for CPU designs
• Working with RTL and DV teams to recommend System Verilog assertions needed to support CDC/RDC/STA constraints and assumptions
• Highlighting to the RTL team any CDC/RDC issues and recommending solutions to them and educating them on CDC/RDC issues and the importance of structurally safe solutions to each issue
• Responsible for developing, enhancing, and maintaining key STA checks and associated sign-offs for our CPUs including things needed to complement CDC/RDC
• Responsible for debugging vendor tool problems and collaborate with designers to help solve their problems
• Working closely with EDA vendor representatives to drive improvements and new methodologies
• Working closely with RTL, Verification, CAD, and Physical Design teams
Job Tags
Relocation,